__Predictable Multiprocessor Platforms for Embedded Safety Critical Systems__ - addresses the following challenges with respect to the introduction of multicore processors in safety-critical systems:
- model and analyze the timing interference generated by the hardware resources shared between cores (e.g., caches, interconnect and I/O devices);
- propose runtime mechanisms and scheduling solutions to mitigate the unpredictability of COTS multicore processors by controlling the interference between cores;
- develop tools for the automatic system configuration before its deployment.