VVML - Specifying Workflows for Verification & Validation Methods
You can find here the slides for a lecture that I gave in the VALU3S' Summer School on Verification and Validation of Dependable Cyber-Physical Systems, held in Genova, Italy on 18th-20th July 2023 - https://valu3s.eu/summer-school-2023/.
VVML (Verification & Validation Modelling Language) is a modelling language based on UML’s activity diagrams optimised to describe processes where formal methods are applied in concrete systems. This lecture describes an approach to formalise and to reason formally over correctness of workflows described using in VVML. The (informal) guidelines on how to build VVML workflows can be found online:
An interactive tool has been developed to animate the semantics proposed in the slides, and can be found online.
- Source code: https://www.github.com/cister-labs/coreVVML
- Use the tool: https://cister-labs.github.io/coreVVML
José Proença
Assistant Professor
José Proença is an Assistant Professor at Faculty of Science of the University of Porto, and a researcher at the Research Center in Real-Time & Embedded Computing Systems, ISEP, in Portugal. His core research targets coordination aspects and formal methods in the context of Cyber-Physical Systems. He is actively involved in a NextGenerationEU project and in 1 FCT project. He currently belongs to the steering committee of 2 international conferences in fundamental computer science, he chaired the program committee of 6 international research venues with edited proceedings, edited 2 journal volumes, and was the member of 19 program-committees of international venues.